1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device equipped with a reference voltage generating circuit and a step-down circuit that steps down an external power supply voltage externally supplied and produces a step-down voltage equal to a reference voltage generated by the reference voltage generating circuit.
2. Description of the Related Art
In FIG. 1, there is illustrated an essential part of a related semiconductor integrated circuit device. The device shown in FIG. 1 includes a reference voltage generating circuit 1, a VCC power supply line 2, resistors 3 through 5, enhancement type nMOS (n-channel Metal Oxide Semiconductor) transistors 6 and 7, and depletion type pMOS (p-channel MOS) transistors 8 and 9. The reference voltage generating circuit 1 generates a reference voltage VREF. The VCC power supply line carries an external power supply voltage VCC externally supplied.
The device shown in FIG. 1 also includes a step-down circuit 10, which steps down the external power supply voltage VCC externally supplied. The step-down circuit 10 includes a VCC power supply line 11, an enhancement type pMOS transistor 12 serving as a regulator transistor, and an operational amplifier 13. Symbol VIIA denotes a step-down voltage obtained by stepping down the external power supply voltage VCC.
Further, the device shown in FIG. 1 includes an internal circuit 14, which is operated by a power supply voltage which is the step-down voltage VIIA output by the step-down circuit 10.
The reference voltage generating circuit 1 generates the reference voltage VREF equal to 2.times.VTH.sub.n-E +2.times..vertline.VTH.sub.n-D .vertline. where VTH.sub.n-E denotes the threshold voltage of the enhancement type nMOS transistor and VTH.sub.n-D denotes the threshold voltage of the depletion type nMOS transistor.
In the step-down circuit 10, the pMOS transistor 12 steps down the external power supply voltage VCC, and the step-down voltage VIIA obtained at the drain of the pMOS transistor 12 is fed back to the inverting input terminal of the operational amplifier 13. The output signal of the operational amplifier 13 controls the gate voltage of the pMOS transistor 12 so that the step-down voltage VIIA equal to the reference voltage VREF can be produced.
It will be noted that the pMOS transistors 8 and 9 forming the reference voltage generating circuit 1 are supplied with the external power supply voltage VCC, while the transistors forming the internal circuit 14 are supplied with the step-down voltage VIIA. The breakdown voltage of the nMOS transistors 8 and 9 will be reduced and the stable operation thereof may not be ensured, if the gate oxide films of the nMOS transistors 8 and 9 are formed by the same process as the gate oxide films of the transistors forming the internal circuit 14 so that the gate oxide films of the nMOS transistors 8 and 9 have the same thickness as that of the transistors forming the internal circuit 14.
If the gate oxide films of the nMOS transistors 8 and 9 are formed so that they are thicker than those of the transistors forming the internal circuit 14, the stability of the operation of the reference voltage generating circuit 1 can be improved. However, the production process will become complex.
There is a case where another reference voltage different from the reference voltage VIIA internally produced is externally applied to the semiconductor integrated circuit device equipped with the reference voltage generating circuit 1 when testing it. In such a case, if the reference voltage externally supplied is higher than the reference voltage VREF generated by the reference voltage generating circuit 1, the externally supplied reference voltage gets over the reference voltage VREF generated by the reference voltage generating circuit 1. Hence, the externally supplied reference voltage higher than the reference voltage VREF can be supplied to the non-inverting input terminal of the operational amplifier 13.
If the reference voltage externally supplied is lower than the reference voltage VREF generated by the reference voltage generating circuit 1, the externally supplied reference voltage cannot get over the reference voltage VREF. Hence, it is impossible to supply, when testing the device, the inverting input terminal of the operational amplifier 13 with the externally supplied reference voltage lower than the reference voltage VREF.